Thermal Bound Placement With Wire Length Consideration for Standard Cells in VLSI

Due to increase in MOS scaling, frequency and bandwidth of high performance CMOS VLSI circuits, on-chip consumed power is enhanced. It creates an important role in both switching and dc power dissipation. This dissipated power is usually rehabilitated into degenerated heat, affecting the performance and consistency of a chip. In this paper we contribute: an algorithm for thermal bound placement of standard cells with wire length consideration to minimize the probable occurrence of hot spots. Experimental results generated by using standard benchmark instances are quite impressive.